This application claims priority to Korean Patent Application No. 10-2002-0073358, filed on Nov. 25, 2002, the entire contents of which are incorporated herein by reference.
The present invention generally relates to circuits and methods for operating integrated circuit memory devices and, more particularly, to circuits and methods for testing integrated circuit memory devices.
The manufacture of integrated circuit (semiconductor) memory devices generally includes testing the memory devices using an external tester. In testing a semiconductor memory device, a test pattern can be written to (and read back from) memory cells of the memory device to determine whether the memory cells are operating properly. If the data read from a memory cell is equal to the test pattern written to the memory cell, the memory cell is determined to be xe2x80x9cgoodxe2x80x9d whereas if the data read from the memory cell is not equal to the test pattern written to the memory cell, the memory cell is determined to be xe2x80x9cdefective.xe2x80x9d
Generally, it is preferable for xe2x80x9chigh speedxe2x80x9d memory devices to be tested using a high frequency clock, but the cost of a high frequency crystal oscillator used to generate the high frequency clock signal may be prohibitive.
It is known to test high speed memory devices using a xe2x80x9clow frequency testerxe2x80x9d that provides low frequency clock signals to the memory device. In this conventional approach, two pins of the memory device to be tested are dedicated to receiving two low frequency clock signals generated by the low frequency tester. The two low frequency clocks can be out of phase by about 90xc2x0 which can be combined to create a high frequency clock internal to the memory device. However, in some cases, such as in the case where the number of input/output (IO) is as many as X32, it may be difficult to dedicate these pins to receiving the clock. In particular, a memory device that requires many signals, data, etc. for operation may be xe2x80x9cpin limitedxe2x80x9d such that all of the pins of the device are already required for other operations. Furthermore, if the tester is required to provide all these control, data, etc. signals for operation of the memory device, it may be difficult for the tester to provide all of the control, data, etc. in addition to the multiple clocks that may also be required, which may affect productivity and cost of operating the tester.
Embodiments according to the invention can provide high frequency integrated circuit memory devices that can be tested using low frequency testers. Pursuant to these embodiments, an integrated circuit memory device can include a test pattern data generator circuit that is configured to generate an extended test pattern data based on test pattern data provided to the memory device during a test mode of the memory device and configured to provide the extended test pattern data and the test pattern data during a test mode of the memory device.
In some embodiments according to the present invention, the test pattern data generator circuit can include a first test pattern data generator circuit and a second test pattern data generator circuit that is configured to generate second extended test pattern data based on second test pattern data provided to the memory device during the test mode. An output buffer circuit can be configured to output the first test pattern data, the first extended test pattern data, the second test pattern data, and the second extended test pattern data.
In some embodiments according to the present invention, the output buffer circuit can be configured to output the first test pattern data, the first extended test pattern data, the second test pattern data, and the second extended test pattern data serially in time synchronous with a clock having a frequency that is greater than a frequency at which the first and second test pattern data are provided to the memory device.
In some embodiments according to the present invention, the test pattern data is provided to the memory device at a first frequency and the extended test pattern data and the test pattern data are output serially in time at a second frequency that is greater than the first frequency. In some embodiments according to the present invention, the test pattern data generator circuit generates the extended test pattern data by at least one of replicating the test pattern data, inverting the test pattern data, and randomizing the test pattern data.
In some embodiments according to the present invention, the test pattern generator circuit can include a first transmission gate configured to selectively output the test pattern data in response to a mode register set signal associated with the test mode based on a state of an inverted mode register set signal electrically connected thereto. A first inverter circuit can be configured to invert the test pattern data to provide inverted test pattern data. A second transmission gate can be configured to selectively output the inverted test pattern data based on the state of the mode register set signal. A second inverter circuit can be configured to invert the mode register set signal to provide the inverted mode register set signal that is electrically connected to the first transmission gate.
In other embodiments according to the present invention, methods of generating extended test data in an integrated circuit memory device can include generating an extended test pattern data based on test pattern data provided to the memory device during a test mode of the memory device and providing the extended test pattern data and the test pattern data during a test mode of the memory device.